SH74582_15 Datasheet, PDF (10/14 Pages) Renesas Technology Corp – RENESAS MCU

SH74582
Appendix D
Section 28 Direct RAM Input Interface (DRI)
Appendix D.1
28.1 Overview
Table 28.1 lists the overview of the DRIi modules.
Appendix D
Table 28.1 DRIi Overview
Item
Number of channels
Operating frequency
Transfer method
Access areas
Maximum transfer rate
Minimum data acquisition
period
Data acquisition bus width
Event counter
Bank switching function
Data acquisition edges
Acquisition timing adjustment
function
Decimation control function
Description
3 channels
80 MHz (when PAck = 80 MHz)
Clock synchronous parallel input
All SHwyRAM areas (up to 512 Kbytes)
80 Mbytes/second (when the DRIi operating frequency is 80 MHz)
The following are the minimum periods when the DRIi operating frequency is 80 MHz.
43.75 ns (special mode disabled and the input data bus width is 8 or 16 bits)
25 ns (special mode enabled)
8 or 16 bits
16 bits  6 counters (DEC5 to DEC0)
Two banks can be specified as the data storage destination in SHwyRAM
Either rising edges, falling edges, or both edges can be selected
Sets the time between detection of the data acquisition edge and the acquisition
operation
Data can be acquired selectively using an event counter (DEC5 to DEC0)
R01DS0240EJ0111 Rev.1.11
Feb 18, 2015
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