SH74582_15 Datasheet, PDF (5/14 Pages) Renesas Technology Corp – RENESAS MCU

SH74582
Appendix B
Appendix B.1
Section 11 Address Space
For details on the P0/U0 area to the P4 area, see figures 11.2 to 11.6.
Appendix B
32-bit virtual address space
via CPU
H’0000 0000
H'000F FFFF
H’0010 0000
H'03FF FFFF
H’0400 0000
H'07FF FFFF
H’0800 0000
H'0BFF FFFF
H’0C00 0000
H'0FFF FFFF
H’1000 0000
P0/U0 area
(512 Mbytes)
H'13FF FFFF
H’1400 0000
H'17FF FFFF
H’1800 0000
H'1807 FFFF
H’1808 0000
H'1BFF FFFF
H’1C00 0000
H'1FFF FFFF
Area 0
Area 1
29-bit physical address space
Single chip
Internal ROM
(1 Mbyte)
Reserved
Area 2
Area 3
Reserved
Area 4
Area 5
Area 6
Area 7
SHwyRAM
(512Kbytes)
Reserved
Reserved
Note:
The CPU, DMAC, AUDR, and other modules cannot access a reserved area.
But the CPU can access area 7 as a control register area using the MMU.
Figure 11.2 Address Space (P0/U0 Area)
R01DS0240EJ0111 Rev.1.11
Feb 18, 2015
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