SH74582_15 Datasheet, PDF (12/14 Pages) Renesas Technology Corp – RENESAS MCU

SH74582
Appendix D
Appendix D.3
28.3.24 DRIi Address Counters 0 and 1 (DRIiADR0CT and DRIiADR1CT)
The DRIiADR0CT and DRIiADR1CT counters are provided to specify bits A18 to A2 of the address in SHwyRAM
that is the DRIi module transfer destination. Bits A31 to A19 are fixed at "0". These counters are incremented by "4"
each time a DRIi transfer completes. There are two DRIi address counter operating modes, and applications can select
the mode with the DRIi transfer control register (DRIiTRMCNT) ADMD bit. See the documentation of the DRIi
transfer control register (DRIiTRMCNT) for details.
Notes: 


If a DRIi address counter value is a value other than an area in which SHwyRAM is located, the DRIi
module will behave as though the DRIi transfers complete, but no writes of the acquired data will be
performed whatsoever.
A DRIi address counter is incremented by "4" when a DRIi transfer completed. This is performed for the
one that is active at that time according to the setting of the DRIi transfer control register (DRIiTRMCNT)
ADSL (address counter selection) bit.
These registers must only be rewritten in the state where a DRIi transfer counter (DRIiTRMCT) underflow
has occurred (the counter is stopped at the value H'0000 0000).
DRI0 Address Counters 0 (DRI0ADR0CT)
DRI1 Address Counters 0 (DRI1ADR0CT)
DRI2 Address Counters 0 (DRI2ADR0CT)
<P4 address: location H'FFBF C028>
<P4 address: location H'FFBF D028>
<P4 address: location H'FFBF E028>
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
DRIAD0
After Reset: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DRIAD0
⎯⎯
After Reset: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRI0 Address Counters 1 (DRI0ADR1CT)
DRI1 Address Counters 1 (DRI1ADR1CT)
DRI2 Address Counters 1 (DRI2ADR1CT)
<P4 address: location H'FFBF C030>
<P4 address: location H'FFBF D030>
<P4 address: location H'FFBF E030>
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
DRIAD1
After Reset: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DRIAD1
⎯⎯
After Reset: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Abbreviation After Reset R W
<After Reset: H'0000 0000>
Description
31 to 19 
All 0
0 0 Reserved Bits
18 to 2 DRIADn
All 0
These bits are always read as "0". The write value should always be "0".
R W Destination Address Bits 18 to 2 (512-Kbyte area)
1, 0

All 0
0 0 Reserved Bits
These bits are always read as "0". The write value should always be "0".
Legend: n = 0 or 1
R01DS0240EJ0111 Rev.1.11
Feb 18, 2015
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