H8S2339 Datasheet, PDF (733/1244 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 16 A/D Converter (12 Analog Input Channel Version)
16.2 Register Descriptions
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — —
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
:R R R R R R R R R R R R R R R R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
16.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
16.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 16.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 1)
Channel Set 1 (CH3 = 0)
Group 0
(CH2 = 0)
AN0
AN1
AN2
AN3
Group 1
(CH2 = 1)
AN4
AN5
AN6
AN7
Group 0
(CH2 = 0)
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Group 1
(CH2 = 1)
AN12
AN13
AN14
AN15
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev.4.00 Sep. 07, 2007 Page 703 of 1210
REJ09B0245-0400