H8S2339 Datasheet, PDF (13/1244 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

4.1.2 Exception Handling Operation............................................................................. 88
4.1.3 Exception Vector Table ....................................................................................... 88
4.2 Reset ................................................................................................................................. 90
4.2.1 Overview.............................................................................................................. 90
4.2.2 Reset Sequence .................................................................................................... 90
4.2.3 Interrupts after Reset............................................................................................ 91
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 91
4.3 Traces................................................................................................................................ 92
4.4 Interrupts ........................................................................................................................... 93
4.5 Trap Instruction................................................................................................................. 94
4.6 Stack Status after Exception Handling.............................................................................. 94
4.7 Notes on Use of the Stack ................................................................................................. 95
Section 5 Interrupt Controller .......................................................................................... 97
5.1 Overview........................................................................................................................... 97
5.1.1 Features................................................................................................................ 97
5.1.2 Block Diagram..................................................................................................... 98
5.1.3 Pin Configuration................................................................................................. 99
5.1.4 Register Configuration......................................................................................... 99
5.2 Register Descriptions ........................................................................................................ 100
5.2.1 System Control Register (SYSCR) ...................................................................... 100
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 101
5.2.3 IRQ Enable Register (IER) .................................................................................. 102
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 103
5.2.5 IRQ Status Register (ISR).................................................................................... 104
5.3 Interrupt Sources ............................................................................................................... 105
5.3.1 External Interrupts ............................................................................................... 105
5.3.2 Internal Interrupts................................................................................................. 107
5.3.3 Interrupt Exception Vector Table ........................................................................ 107
5.4 Interrupt Operation............................................................................................................ 113
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 113
5.4.2 Interrupt Control Mode 0 ..................................................................................... 116
5.4.3 Interrupt Control Mode 2 ..................................................................................... 118
5.4.4 Interrupt Exception Handling Sequence .............................................................. 120
5.4.5 Interrupt Response Times .................................................................................... 122
5.5 Usage Notes ...................................................................................................................... 123
5.5.1 Contention between Interrupt Generation and Disabling..................................... 123
5.5.2 Instructions That Disable Interrupts..................................................................... 124
5.5.3 Times when Interrupts Are Disabled ................................................................... 124
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 124
Rev.4.00 Sep. 07, 2007 Page xiii of xxx