H8S2339 Datasheet, PDF (1048/1244 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Appendix B Internal I/O Registers
TIOR3L—Timer I/O Control Register 3L
H'FE83
TPU3
Bit
:
Initial value :
Read/Write :
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
TGR3C I/O Control
0 0 0 0 TGR3C Output disabled
1
1
0
is output
compare
register*¹
Initial output
0 output
is
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3C Capture input
is input source is
1 _{capture TIOCC3 pin}
1 * ^register*1
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1**
Capture input _{Input capture at TCNT4 count-up/}
source is channel
4/count clock
count-down
* : Don't care
Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
this setting is invalid and input capture/output compare does not occur.
TGR3D I/O Control
0 0 0 0 TGR3D Output disabled
1
1
0
is output
compare
register
Initial output is 0
output
0 output at compare match
1 output at compare match
*2
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 0 0 0 TGR3D Capture input Input capture at rising edge
is input source is
1 _{capture TIOCD3 pin}
Input capture at falling edge
1 * ^register
*2
Input capture at both edges
1**
Capture input _{Input capture at TCNT4 count-up/}
source is channel
4/count clock
count-down*¹
Notes:
* : Don't care
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the
TCNT4 count clock, this setting is invalid and input capture does not occur.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare does not occur.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Rev.4.00 Sep. 07, 2007 Page 1018 of 1210
REJ09B0245-0400