H8S2339 Datasheet, PDF (1042/1244 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Appendix B Internal I/O Registers
B.3 Functions
MRA—DTC Mode Register A
H'F800 to H'FBFF
DTC
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
SM1 SM0 DM1 DM0 MD1 MD0 DTS
Sz
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
—
—
—
—
—
—
—
—
DTC Data
Transfer Size
0 Byte-size
transfer
1 _Word-size
transfer
DTC Transfer Mode Select
0 Destination side is repeat
area or block area
DTC Mode
1 _{Source side is repeat area}
or block area
0 0 Normal mode
1 Repeat mode
1 0 Block transfer mode
1—
Destination Address Mode
0 — _{DAR is fixed}
1 0 _{DAR is incremented after a transfer}
(by +1 when Sz = 0; by +2 when Sz = 1)
1 _{DAR is decremented after a transfer}
(by –1 when Sz = 0; by –2 when Sz = 1)
Source Address Mode
0 — _{SAR is fixed}
1 0 _{SAR is incremented after a transfer}
(by +1 when Sz = 0; by +2 when Sz = 1)
1 _{SAR is decremented after a transfer}
(by –1 when Sz = 0; by –2 when Sz = 1)
Rev.4.00 Sep. 07, 2007 Page 1012 of 1210
REJ09B0245-0400