HD404654 Datasheet, PDF (70/111 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404654 Series
External clock mode
STS wait state
(Octal counter = 000,
Transmit clock disabled)
00 MCU reset
SM1A write 04
01 STS instruction
06 SM1A write (IFS1 ^← 1)
Transmit clock wait state
(Octal counter = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS1 ^← 1)
Transfer state
(Octal counter = 000)
Internal clock mode
SM1A write
18
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
Continuous transmit
clock output state
(PMRA 0, 1 = 0, 0)
SM1A write 14
11 STS instruction
13 8 transmit clocks
16 SM1A write (IFS1←1)
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
12 Transmit clock
15
STS instruction (IFS1 ← 1)
Transfer state
(Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 53 Serial Interface State Transitions
• STS wait state: Serial interface 1 enters STS wait state by MCU reset (00, 10 in figure 53). In STS wait
state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is the period between STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
serial interface in transfer state. However, note that if continuous clock output mode is selected in
internal clock mode, the serial interface does not enter transfer state but enters continuous clock output
state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
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