HD404654 Datasheet, PDF (24/111 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404654 Series
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 9.
Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
0
1
Interrupt Request
No
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 10.
Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
11.
Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD
0
1
Interrupt Request
No
Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 12.
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