HD404654 Datasheet, PDF (41/111 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404654 Series
Pins D₁₂ and D₁₃ are multiplexed with peripheral function pins STOPC and INT₀, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 24).
R Ports (R0₀, R1₀–R4₃, RD₀, RD₁, RE₀): 17 input/output pins and 3 input pins addressed in 4-bit units.
Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB
instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the
output buffers of the R ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034) that
are mapped to memory addresses (figure 23).
Pin R0₀ is multiplexed with peripheral pin INT₁. The peripheral function mode of this pins is selected by
bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 25).
Pins R3₁–R3₂ are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function
modes of these pins are selected by bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014),
and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 26, and 27).
Pin R4₀ is multiplexed with peripheral pin EVND. The peripheral function mode of this pins is selected by
bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 24).
Pins R4₁–R4₃ are multiplexed with peripheral pins SCK₁, SI₁, and SO₁, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 28 and 29.
Ports RD₀ and RD₁ are multiplexed with peripheral function pins COMP₀ and COMP₁, respectively. The
function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018), as
shown in figure 30.
Port RE₀ is multiplexed with peripheral function pin VC_ref. While functioning as VC_ref, do not use this pin
as an R port at the same time, otherwise, the MCU may malfunction.
Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D₁₂ and D₁₃. The on/off status of
all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin—enabling on/off control of that pin alone (table 19 and figure 31).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V_CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to V_CC by
their pull-up MOS transistors or by resistors of about 100 kΩ or pulled down to GND by their pull-down
MOS transistors.
39