HD404654 Datasheet, PDF (53/111 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404654 Series
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.
• Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).
 Toggle
 0 output
 1 output
 PWM output
By selecting the timer output mode, pin R3₁/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
 Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input
after timer C has reached $FF. By using this function and the reload timer function, clock signals
can be output at a required frequency for the buzzer. The output waveform is shown in figure 36.
 PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 36.
 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after
timer C has reached $FF. Note that this function must be used only when the output level is high.
 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer
C has reached $FF. Note that this function must be used only when the output level is low.
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