PD46185084B_15 Datasheet, PDF (7/39 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Description
Symbol
A
Type
Input
D0 to Dxx Input
Q0 to Qxx Output
R#
Input
W#
Input
BWx#
NWx#
Input
K, K#
Input
C, C#
Input
(1/2)
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of four words
(two clock periods of bus activity). These inputs are ignored when device is deselected,
i.e., NOP (R# = W# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location
of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to
K and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C
and C# (or K and K#), depending on the R# command. See Pin Arrangement for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Read: When LOW this input causes the address inputs to be registered and
a READ cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a READ command (R# = LOW) is input, an input of R# on the subsequent
rising edge of K is ignored.
Synchronous Write: When LOW this input causes the address inputs to be registered and
a WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a WRITE command (W# = LOW) is input, an input of W# on the subsequent
rising edge of K is ignored.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their
respective byte or nibble to be registered and written during WRITE cycles. These signals
must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Pin Arrangement for signal to data
relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first and third output
data. The rising edge of C is used as the output reference for second and fourth output
data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be
guaranteed unless C and C# are fixed to HIGH (i.e. toggle of C and C#).
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
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