PD46185084B_15 Datasheet, PDF (21/39 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Read and Write Cycle
Parameter
Symbol
-E33, -E33Y
-E40, -E40Y
Unit
Note
(300 MHz)
(250 MHz)
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time
TKHKH
3.3
8.4
4.0
8.4
ns
1
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#) TKC var
0.2
0.2
ns
2
Clock HIGH time (K, K#, C, C#) TKHKL
1.32
1.6
ns
Clock LOW time (K, K#, C, C#) TKLKH
1.32
1.6
ns
Clock HIGH to Clock# HIGH
TKHK#H
1.49
1.8
ns
(K → K#, C → C#)
Clock# HIGH to Clock HIGH
TK#HKH
1.49
1.8
ns
(K# → K, C# → C)
Clock to data clock
TKHCH
0
1.45
0
1.8
ns
(K → C, K# → C#)
PLL lock time (K, C)
TKC lock
20
20
μs
3
K static to PLL reset
TKC reset
30
30
ns
4
Output Times
CQ HIGH to CQ# HIGH
TCQHCQ#H 1.24
1.55
ns
5
(CQ → CQ#)
CQ# HIGH to CQ HIGH
TCQ#HCQH 1.24
1.55
ns
5
(CQ# → CQ)
C, C# HIGH to output valid
TCHQV
0.45
0.45
ns
C, C# HIGH to output hold
TCHQX
–0.45
–0.45
ns
C, C# HIGH to echo clock valid TCHCQV
0.45
0.45
ns
C, C# HIGH to echo clock hold TCHCQX –0.45
–0.45
ns
CQ, CQ# HIGH to output valid TCQHQV
0.27
0.3
ns
6
CQ, CQ# HIGH to output hold TCQHQX –0.27
–0.3
ns
6
C HIGH to output High-Z
TCHQZ
0.45
0.45
ns
C HIGH to output Low-Z
TCHQX1 –0.45
–0.45
ns
Setup Times
Address valid to K rising edge
TAVKH
0.4
0.5
ns
7
Control inputs (R#, W#) valid to TIVKH
0.4
0.5
ns
7
K rising edge
Data inputs and write data
TDVKH
0.3
0.35
ns
7
select
inputs (BWx#, NWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
TKHAX
0.4
0.5
ns
7
K rising edge to control inputs
TKHIX
0.4
0.5
ns
7
(R#, W#) hold
K, K# rising edge to data inputs TKHDX
0.3
0.35
ns
7
and write data select inputs
(BWx#, NWx#) hold
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 21 of 38