PD46185084B_15 Datasheet, PDF (31/39 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
EXTEST
0
1
IDCODE
0
1
SAMPLE-Z
0
1
SAMPLE
0
1
BYPASS
0
1
Output Pin Status
CQ,CQ#
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Q
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
There are three statuses:
Boundary Scan
Register
CAPTURE
Register
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
Update
Register
Update
SRAM
Output
QDR
Pad
High-Z
SRAM
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 31 of 38