HN58X2402SFPIAG Datasheet, PDF (7/18 Pages) Renesas Technology Corp – Two-wire serial interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit)

HN58X2402SFPIAG/HN58X2404SFPIAG
Device Address (A0, A1, A2)
UP to eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to
different combinations. The levels on these pins are compared with the device address code which are input through
the SDA pin. The device is selected if the compare is successfully done. These pins are internally pulled-down to V_SS.
The device read these pins as Low if unconnected. As for 4k, it is unnecessary for the A0 pin to be connected because
the corresponding device address code is used as memory address a8.
Pin Connections for A0 to A2
Pin connection
Memory size Max connect
A2
A1
A0
Notes
number
2k bit
4k bit
8
V_CC/V_SS*¹ V_CC/V_SS V_CC/V_SS
4
V_CC/V_SS V_CC/V_SS
×*² Use A0 for memory address a8
Notes: 1. “V_CC/V_SS” means that the device address pins are connected to V_CC or V_SS. These pins are V_SS if
unconnected.
2. × = Don’t care (Open is also approval.)
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protections feature is enabled and operates as shown in the
following table. When the WP is low, write operations for all memory array are allowed. The read operation is always
activated irrespective of the WP pin status. The WP pin is internally pull-down to V_SS. Write operations for all
memory array are allowed if unconnected.
Write Protect Area
WP pin status
V_IH
V_IL
Write protect area
2k bit
4k bit
Entire (2k bit)
Entire (4k bit)
Normal read/write operation
Rev.4.00, Jul.13.2005, page 7 of 16