HN58X2402SFPIAG Datasheet, PDF (15/18 Pages) Renesas Technology Corp – Two-wire serial interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit)

HN58X2402SFPIAG/HN58X2404SFPIAG
Notes
Data protection at V_CC On/Off
When V_CC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset
function to operate correctly.
• SCL and SDA should be fixed to V_CC or V_SS during V_CC on/off. Low to high or high to low transition during V_CC
on/off may cause the trigger for the unintentional programming.
• V_CC should be turned off after the EEPROM is placed in a standby state.
• V_CC should be turned on from the ground level(V_SS) in order for the EEPROM not to enter the unintentional
programming mode.
• V_CC turn on speed should be longer than 10 µs.
Write/Erase Endurance and Data retention Time
The endurance is 10⁵ cycles in case of page programming and 10⁴ cycles in case of byte programming (1% cumulative
failure rate). The data retention time is more than 10 years when a device is page-programmed less than 10⁴ cycles.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be
careful not to allow noise of width more than 50 ns.
Rev.4.00, Jul.13.2005, page 15 of 16