HN58X2402SFPIAG Datasheet, PDF (4/18 Pages) Renesas Technology Corp – Two-wire serial interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit)

HN58X2402SFPIAG/HN58X2404SFPIAG
AC Characteristics (Ta = −40 to +85°C, V_CC = 1.8 to 5.5 V)
Test Conditions
• Input pules levels:
 V_IL = 0.2 × V_CC
 V_IH = 0.8 × V_CC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × V_CC
• Output load: TTL Gate + 100 pF
Parameter
Symbol
Min
Typ
Max
Clock frequency
f_SCL


400
Clock pulse width low
t_LOW
1200


Clock pulse width high
t_HIGH
600


Noise suppression time
t_I


50
Access time
t_AA
100

900
Bus free time for next mode
t_BUF
1200


Start hold time
t_HD.STA
600


Start setup time
t_SU.STA
600


Data in hold time
t_HD.DAT
0


Data in setup time
t_SU.DAT
100


Input rise time
t_R


300
Input fall time
t_F


300
Stop setup time
t_SU.STO
600


Data out hold time
t_DH
50


Write protect hold time
t_HD.WP
1200


Write protect setup time
t_SU.WP
0


Write cycle time
V_CC = 2.7 V to 5.5 V
t_WC


10
V_CC = 1.8 V to 2.7 V
t_WC


15
Notes: 1. This parameter is sampled and not 100% tested.
2. t_WC is the time from a stop condition to the end of internally controlled write cycle.
Unit Notes
kHz
ns
ns
ns
1
ns
ns
ns
ns
ns
ns
ns
1
ns
1
ns
ns
ns
ns
ms
2
ms
2
Rev.4.00, Jul.13.2005, page 4 of 16