HN58X2402SFPIAG Datasheet, PDF (6/18 Pages) Renesas Technology Corp – Two-wire serial interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit)

HN58X2402SFPIAG/HN58X2404SFPIAG
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.
Serial Input/Output data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-
drain driven structure. Use proper resistor value for your system by considering V_OL, I_OL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be
completed during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Data
change
Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.
Rev.4.00, Jul.13.2005, page 6 of 16