HD74LV4040A Datasheet, PDF (7/11 Pages) Hitachi Semiconductor – 12-stage Binary Counter

HD74LV4040A
Switching Characteristics (Cont.)
Item
Maximum
clock frequency
Propagation
delay time
Propagation
delay time skew
Setup time
Symbol
f_max
t_PLH/t_PHL
t_PHL
∆t_pd
Ta = 25°C
Min Typ
150 210
95 125
— 4.8
— 6.3
— 5.6
— 7.1
— 1.6
t_SU
5.0 —
Max
—
—
7.3
9.3
8.6
10.6
3.1
—
Ta = –40 to 85°C
Min
Max
125
—
80
—
1.0
8.5
1.0
10.5
1.0
10.0
1.0
12.0
—
3.5
5.0
—
Test
Unit Conditions
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 50 pF
ns
Pulse width
t_w
5.0 — — 5.0
—
ns
5.0 — — 5.0
—
V_CC = 5.0 ± 0.5 V
FROM TO
(Input) (Output)
CLK
Q₁
CLR
Q_n
Q_n + 1
CLR inactive before
CLK ↓
CLK high or low
CLR high
Operating Characteristics
C_L = 50 pF
Ta = 25°C
Item
Symbol V_CC = (V) _Min
Typ
Max
Unit Test Conditions
Power dissipation capacitance C_PD
3.3
—
17.3
—
pF
f = 10 MHz
5.0
—
19.0
—
Noise Characteristics
Item
Quiet output, maximum
dynamic V_OL
Quiet output, minimum
dynamic V_OL
Quiet output, minimum
dynamic V_OH
High-level dynamic input
voltage
Low-level dynamic input
voltage
Symbol V_CC = (V)
V_{OL (P)}
3.3
Ta = 25°C
Min
Typ
—
0.4
V_{OL (V)}
3.3
—
–0.5
V_{OH (V)}
3.3
—
3.0
V_{IH (D)}
3.3
2.31
—
V_{IL (D)}
3.3
—
—
Max
0.8
–0.8
—
—
0.99
C_L = 50 pF
Unit Test Conditions
V
V
V
V
V
Rev.2.00 Jul. 20, 2004 page 7 of 10