HD74LV4040A Datasheet, PDF (1/11 Pages) Hitachi Semiconductor – 12-stage Binary Counter

HD74LV4040A
12-stage Binary Counter
REJ03D0337–0200Z
(Previous ADE-205-282 (Z))
Rev.2.00
Jul. 20, 2004
Description
The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the
input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-
speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV4040AFPEL
SOP–16 pin (JEITA) FP–16DAV
FP
HD74LV4040ARPEL
SOP–16 pin (JEDEC) FP–16DNV
RP
HD74LV4040ATELL
TSSOP–16 pin
TTP–16DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
CLK
↑
↓
X
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
CLR
L
L
H
Output
Q_n
Remains unchanged
Changed
All outputs low
Rev.2.00 Jul. 20, 2004 page 1 of 10