HD74LV4040A Datasheet, PDF (6/11 Pages) Hitachi Semiconductor – 12-stage Binary Counter

HD74LV4040A
Switching Characteristics
Item
Maximum
clock frequency
Propagation
delay time
Propagation
delay time skew
Setup time
Symbol
f_max
t_PLH/t_PHL
t_PHL
∆t_pd
Ta = 25°C
Min Typ
50 90
30 60
— 10.0
— 12.7
— 9.9
— 11.8
— 3.0
t_SU
7.0 —
Max
—
—
16.0
19.6
15.4
18.0
5.5
—
Ta = –40 to 85°C
Min
Max
40
—
25
—
1.0
18.3
1.0
22.2
1.0
17.5
1.0
20.4
—
6.3
7.0
—
Test
Unit Conditions
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 50 pF
ns
Pulse width
t_w
7.0 — — 7.0
—
ns
7.0 — — 7.0
—
Item
Maximum
clock frequency
Propagation
delay time
Propagation
delay time skew
Setup time
Symbol
f_max
t_PLH/t_PHL
t_PHL
∆t_pd
Ta = 25°C
Min Typ
75 140
55 80
— 7.5
— 10.0
— 8.3
— 10.8
— 2.4
t_SU
5.0 —
Max
—
—
11.9
15.4
12.8
16.3
4.4
—
Ta = –40 to 85°C
Min
Max
70
—
50
—
1.0
14.0
1.0
17.5
1.0
15.0
1.0
18.5
—
5.0
5.0
—
Test
Unit Conditions
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 50 pF
ns
Pulse width
t_w
5.0 — — 5.0
—
ns
5.0 — — 5.0
—
V_CC = 2.5 ± 0.2 V
FROM TO
(Input) (Output)
CLK
Q₁
CLR
Q_n
Q_n+1
CLR inactive before
CLK ↓
CLK high or low
CLR high
V_CC = 3.3 ± 0.3 V
FROM TO
(Input) (Output)
CLK
Q₁
CLR
Q_n
Q_n+1
CLR inactive before
CLK ↓
CLK high or low
CLR high
Rev.2.00 Jul. 20, 2004 page 6 of 10