H8SX1657 Datasheet, PDF (636/892 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 Serial Communication Interface (SCI)
14.7.6 Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data can
be re-transmitted. Figure 14.26 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
re-transferred from TDR to TSR allowing automatic data retransmission.
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1.
4. In this case, one frame of data is determined to have been transmitted including re-transfer, and
the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in
SCR is set to 1. Writing transmit data to TDR starts transmission of the next data.
Figure 14.28 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DMAC or DTC. In
transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a
TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DMAC or DTC by
a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a
source of DMAC or DTC activation beforehand. The TDRE and TEND flags are automatically
cleared to 0 at data transfer by the DMAC or DTC. If an error occurs, the SCI automatically re-
transmits the same data. During re-transmission, the TEND flag remains as 0, thus not activating
the DMAC or DTC. Therefore, the SCI and DMAC or DTC automatically transmit the specified
number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag
is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to
enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DMAC or DTC, be sure to set and enable the DMAC
or DTC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller
(DMAC), and for DTC settings, see section 8, Data Transfer Controller (DTC).
Rev. 2.00 Jun. 28, 2007 Page 612 of 864
REJ09B0341-0200