H8SX1657 Datasheet, PDF (506/892 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10 Usage Notes
10.10.1 Module Stop State Setting
Operation of the TPU can be disabled or enabled using the module stop control register. The initial
setting is for operation of the TPU to be halted. Register access is enabled by clearing the module
stop state. For details, refer to section 20, Power-Down Modes.
10.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.45 shows the input clock
conditions in phase counting mode.
Phase
difference
Phase
difference
Overlap
Overlap
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Note: Phase difference, Overlap ≥ 1.5 states
Pulse width ≥ 2.5 states
Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 2.00 Jun. 28, 2007 Page 482 of 864
REJ09B0341-0200