H8SX1657 Datasheet, PDF (480/892 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
(b) When TGR is an input capture register
Figure 10.16 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges
have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 10.16 Example of Buffer Operation (2)
Rev. 2.00 Jun. 28, 2007 Page 456 of 864
REJ09B0341-0200