H8S-2276 Datasheet, PDF (611/869 Pages) Renesas Technology Corp – Single-Chip Microcomputer

External Clock: The external clock signal should have the same frequency as the system clock
(ø).
Table 18.4 and figure 18.6 show the input conditions for the external clock.
Table 18.4 External Clock Input Conditions
Item
External clock input low pulse
width
External clock input high pulse
width
External clock rise time
External clock fall time
Clock low pulse width level
Clock high pulse width level
Symbol
t _EXL
F-ZTAT Version
V_CC = 2.7 V to 3.6 V
Min
Max
Unit
30
—
ns
Conditions
Figure 18.6
t _EXH
30
—
ns
t _EXr
—
7
ns
t _EXf
—
7
ns
t _CL
0.4
0.6
t_cyc ø ≥ 5 MHz Figure 20.3
80
—
ns ø < 5 MHz
t _CH
0.4
0.6
t _cyc
ø ≥ 5 MHz
80
—
ns ø < 5 MHz
The external clock input conditions when the duty adjustment circuit is not used are shown in table
18.5 and figure 18.6. When the duty adjustment circuit is not used, the ø output waveform
depends on the external clock input waveform, and so no restrictions apply.
Table 18.5 External Clock Input Conditions when the Duty Adjustment Circuit is not Used
F-ZTAT Version
Item
V_CC = 2.7 V to 3.6 V
Symbol Min
Max
Unit Conditions
External clock input low pulse
t _EXL
37
—
ns Figure 18.6
width
External clock input high pulse t_EXH
37
—
ns
width
External clock rise time
t _EXr
—
7
ns
External clock fall time
t _EXf
—
7
ns
Note: When duty adjustment circuit is not used, the maximum frequency decreases according to
the input waveform. (Example: When t_EXL = t_EXH = 50 ns, and t_EXr = t_EXf = 10 ns, clock cycle
time = 120 ns; therefore, maximum operating frequency = 8.3 MHz)
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