H8S-2276 Datasheet, PDF (374/869 Pages) Renesas Technology Corp – Single-Chip Microcomputer

• TCSR1
Bit
:
7
OVF
Initial value :
0
R/W
: R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
Note: * Only 0 can be written, to clear the flag.
4
PSS
0
R/W
3
RST/NMI
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 12.2.5, Notes on Register Access.
Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
(Initial value)
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR when OVF = 1, then write 0 in OVF*
1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Note: * When the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit
while it is 1 at least twice.
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