H8S-2276 Datasheet, PDF (288/869 Pages) Renesas Technology Corp – Single-Chip Microcomputer

10.2.3 Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Bit
:
Initial value :
R/W
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Channel 0: TIOR0L
Bit
:
7
Initial value :
R/W
:
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR
registers, two for channel 0, and one each for channels 1 and 2. The TIOR registers are initialized
to H'00 by a reset, and in hardware standby mode.
Care is required since TIOR is affected by the TMDR setting. The initial output specified by
TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in
PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
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