H8S39 Datasheet, PDF (604/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SAR
Bit 0
FS
0
1
SARX
Bit 0
FSX
0
1
0
1
Operating Mode
I²C bus format
• SAR and SARX slave addresses recognized
I²C bus format
• SAR slave address recognized
• SARX slave address ignored
I²C bus format
• SAR slave address ignored
• SARX slave address recognized
Synchronous serial format
• SAR and SARX slave addresses ignored
(Initial value)
15.2.3 Second Slave Address Register (SARX)
Bit
:7
6
5
4
3
2
1
0
SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
Initial value : 0
0
0
0
0
0
0
1
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
SVAX0, differing from the addresses of other slave devices connected to the I²C bus.
Page 554 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010