H8S39 Datasheet, PDF (1435/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
TCNT0—Timer Counter 0
H'FF74(W), H'FF75(R)
WDT0
Bit
7
6
5
4
3
2
1
0
Initial value 0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Up-counter
Note: TCNT0 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
RSTCSR—Reset Control/Status Register
H'FF76(W), H'FF77(R)
WDT0
Bit
7
6
5
4
3
2
1
0
WOVF RSTE RSTS
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write R/(W)* R/W R/W
⎯
⎯
⎯
⎯
⎯
Reset Select
0 Reset
1 Do not set
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2646 are not reset,
but TCNT and TCSR within the WDT are reset.
Watchdog Overflow Flag
0 [Clearing condition]
• Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1 _{[Setting condition]}
• Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Notes: RSTCSR register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
* Can only be written with 0 for flag clearing.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1385 of 1458