H8S39 Datasheet, PDF (220/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
7.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
HWR
Write
LWR
D15 to D8
D7 to D0
Invalid
High
Valid
High impedance
Figure 7-5 Bus Timing for 8-Bit 2-State Access Space
Page 170 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010