R1EV5801MB_15 Datasheet, PDF (6/22 Pages) Renesas Technology Corp – 1M EEPROM (128-Kword × 8-bit)Ready/ Busy and RES function

R1EV5801MB Series
AC Characteristics
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V, 0 V to V_CC (RES pin)
• Input rise and fall time: ≤ 20 ns
• Output load: 1TTL Gate +100 pF
• Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
Parameter
Symbol
Min
Address to output delay
t_ACC
⎯
CE to output delay
t_CE
⎯
OE to output delay
t_OE
10
Address to output hold
t_OH
0
OE (CE) high to output float*¹
t_DF
0
RES low to output float^*1
t_DFR
0
RES to output delay
t_RR
0
Max
250
250
120
⎯
50
350
600
(Ta = -40 to +85°C, V_CC = 2.7 V to 5.5 V)
Unit
ns
ns
ns
ns
ns
ns
ns
Test conditions
CE = OE = V_IL, WE = V_IH
OE = V_IL, WE = V_IH
CE = V_IL, WE = V_IH
CE = OE = V_IL, WE = V_IH
CE = V_IL, WE = V_IH
CE = OE = V_IL, WE = V_IH
CE = OE = V_IL, WE = V_IH
Write Cycle
Parameter
Symbol Min*² Typ Max Unit Test conditions
Address setup time
Address hold time
CE to write setup time (WE controlled)
t_AS
0
⎯
⎯ ns
t_AH
150 ⎯
⎯ ns
t_CS
0
⎯
⎯ ns
CE hold time (WE controlled)
t_CH
0
⎯
⎯ ns
WE to write setup time (CE controlled)
t_WS
0
⎯
⎯ ns
WE hold time (CE controlled)
OE to write setup time
OE hold time
Data setup time
t_WH
0
⎯
t_OES
0
⎯
t_OEH
0
⎯
t_DS
100 ⎯
⎯ ns
⎯ ns
⎯ ns
⎯ ns
Data hold time
t_DH
10
⎯
⎯ ns
WE pulse width (WE controlled)
t_WP
250 ⎯
⎯ ns
CE pulse width (CE controlled)
Data latch time
Byte load cycle
Byte load window
Write cycle time
t_CW
250 ⎯
⎯ ns
t_DL
750 ⎯
⎯ ns
t_BLC
1.0 ⎯
30 μs
t_BL
100 ⎯
⎯ μs
t_WC
⎯
⎯
10*³ ms
Time to device busy
Write start time
Reset protect time
Reset high time*⁵
t_DB
120 ⎯
t_DW
250*⁴ ⎯
t_RP
100 ⎯
t_RES
1
⎯
⎯ ns
⎯ ns
⎯ μs
⎯ μs
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer
driven.
2. Use this device in longer cycle than this value.
3. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically
completes the internal write operation within this value.
4. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100% tested.
6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE.
7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE.
8. See AC read characteristics.
R10DS0209EJ0100 Rev.1.00
Jun 09, 2014
Page 6 of 20