HD404618 Datasheet, PDF (57/91 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

Transmission completion
(IFS ←1)
Interrupts
inhibited
IFS ^← 0
HD404618 Series
SMR write
Yes
IFS = 1 ?
No
Normal termination
Transmit clock
error processing
Figure 34 Transmit Clock Error Detection
Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the
execution of an SMR write or STS instruction during the first period that the transmit clock is low. To
prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port)
before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is
set.
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