HD404618 Datasheet, PDF (13/91 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Bit 3
IM0
0
(IM of INT₀ )
IMTA
1
(IM of timer A)
2
IMTC
(IM of timer C)
3
Not used
Bit 2
IF0
(IF of INT₀ )
IFTA
(IF of timer A)
IFTC
(IF of timer C)
Not used
Bit 1
RSP
(Reset SP bit)
IM1
(IM of INT₁ )
IMTB
(IM of timer B)
IMS
(IM of serial)
Bit 0
IE
(Interrupt enable flag) ^$000
IF1
(IF of INT₁ )
IFTB
(IF of timer B)
$001
$002
IFS
(IF of serial)
$003
32
DTON
Direct transfer on flag
TGSP
(Tone generator
speed flag)
WDON
(Watchdog on flag)
LSON
(Low speed on flag)
$020
$021
Not Used
35
$023
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD
instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IF
RSP
WDON
TGSP
DTON
SEM/SEMD
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
REM/REMD
Allowed
Allowed
Not executed
Allowed
Allowed
TM/TMD
Allowed
Inhibited
Inhibited
Inhibited
Allowed
Note: WDON is always reset in active mode.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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