HD404618 Datasheet, PDF (12/91 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
0
63
64
80
112
959
960
1023
RAM-mapped registers
Memory registers (MR)
LCD display area (32 digits)
Data (144 digits)
$000
$03F
$040
$050
$070
$100
Data (464 digits × 2)*
V = 0 (bank 0)
V = 1 (bank 1)
Not used
Stack (64 digits)
$2CF
$3BF
$3C0
$3FF
$100
0
$000
1
Interrupt control bits area
$001
2
$002
3
4 Port mode register A
5 Serial mode register
(PMRA) W
(SMR) W
$003
$004
$005
6 Serial data register lower (SRL) R/W $006
7 Serial data register upper (SRU) R/W $007
8 _{Timer mode register A (TMA) W $008}
9 ^{Timer mode register B (TMB) W $009}
10 Timer B
11
(TCBL/TLRL) R/W $00A
(TCBU/TLRU) _{R/W $00B}
12 ^{Miscellaneous register (MIS)} W ^$00C
13 Timer mode register C (TMC) W $00D
14 _{Timer C}
15
(TCCL/TCRL) ^{R/W $00E}
(TCCU/TCRU) R/W $00F
16 TG mode register
(TGM) W $010
17 TG control register
(TGC) ^W $011
18 Port mode register B (PMRB) W $012
19 LCD control register
(LCR) W $013
20 LCD mode register
(LMR) W
Not used
$014
32
Register flag area
35
Not used
$020
$023
48 Port R0 DCR
49 Port R1 DCR
(DCR0) W
(DCR1) W
$030
$031
50 Port R2 DCR
(DCR2) W $032
51 Port R3 DCR
(DCR3) W $033
Data (464 digits) Data (464 digits)
V = 0 (bank 0)
V = 1 (bank 1)
Not used
$2CF
Note: Do not use any area labelled “Not used”
* The data area has two banks:
V = 0 (bank 0) and V = 1 (bank 1)
59 Port D ₀–D₃DCR
(DCRB) _W
60 Port D ₄–D₇DCR
(DCRC) _W
61 _{Port D 8–D9DCR}
(DCRD) W
Not used
$03B
$03C
$03D
63 V register
(V-REG) R/W $03F
10
11
R: Read only
14
W: Write only
R/W: Read/write
15
Timer counter B, lower
(TCBL)
Timer counter B, upper
(TCBU)
Timer counter C, lower
(TCCL)
Timer counter C, upper
(TCCU)
R ^{Timer load register B, lower}
(TLRL)
W $00A
R
Timer load register B, upper
(TLRU)
W $00B
R
Timer load register C, lower
(TCRL)
R
Timer load register C, upper
(TCRU)
W $00E
W $00F
Figure 2 RAM Memory Map
10