HD404618 Datasheet, PDF (24/91 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as shown in table 8.
Table 8 Timer A Interrupt Mask
IMTA
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B as shown in
table 9.
Table 9 Timer B Interrupt Request Flag
IFTB
0
1
Interrupt Request
No
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as shown in table 10.
Table 10 Timer B Interrupt Mask
IMTB
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C as shown in
table 11.
Table 11 Timer C Interrupt Request Flag
IFTC
0
1
Interrupt Request
No
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as shown in table 12.
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