H8S2172 Datasheet, PDF (508/572 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

16.2 Operation
16.2.1 Sleep Mode
Transition to Sleep Mode: When the SLEEP instruction is executed while the SSBY bit in
SBYCR is set to 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU's internal registers are retained. Other peripheral functions do not stop.
Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
• Exiting sleep mode by interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting sleep mode by RES pin
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception processing.
• Exiting sleep mode by STBY pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
16.2.2 Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data,
and the states of on-chip peripheral functions other than the SCI, and I/O ports, are retained. In this
mode the oscillator stops, and therefore power consumption is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins IRQ0 to IRQ7), SUSRI interrupt or by means of the RES pin or STBY pin.
• Clearing with an interrupt
When an NMI, IRQ0 to IRQ7 or SUSRI interrupt request signal is input, clock oscillation
starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are
supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling
is started.
When clearing software standby mode with an IRQ0 to IRQ7 or SUSRI interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ7 or SUSRI is generated. Software standby mode cannot be cleared if the interrupt
has been masked on the CPU side.
Rev. 2.00, 03/04, page 474 of 534