H8S2172 Datasheet, PDF (27/572 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 9 8-Bit Timer (TMR)
Figure 9.1 Block Diagram of 8-Bit Timer Module..................................................................... 264
Figure 9.2 Example of Pulse Output........................................................................................... 270
Figure 9.3 Count Timing for Internal Clock Input...................................................................... 271
Figure 9.4 Count Timing for External Clock Input .................................................................... 271
Figure 9.5 Timing of CMF Setting ............................................................................................. 272
Figure 9.6 Timing of Timer Output ............................................................................................ 272
Figure 9.7 Timing of Compare Match Clear............................................................................... 273
Figure 9.8 Timing of Clearance by External Reset..................................................................... 273
Figure 9.9 Timing of OVF Setting.............................................................................................. 274
Figure 9.10 Contention between TCNT Write and Clear ........................................................... 276
Figure 9.11 Contention between TCNT Write and Increment.................................................... 277
Figure 9.12 Contention between TCOR Write and Compare Match.......................................... 278
Section 10 Watchdog Timer (WDT)
Figure 10.1 Block Diagram of WDT .......................................................................................... 283
Figure 10.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 286
Figure 10.3 Interval Timer Mode Operation............................................................................... 287
Figure 10.4 OVF Flag Set Timing .............................................................................................. 287
Figure 10.5 Output Timing of OVF............................................................................................ 288
Figure 10.6 Writing to TCNT and TCSR ................................................................................... 289
Figure 10.7 Conflict between TCNT Write and Increment ........................................................ 290
Section 11 Serial Communication Interface for Boot Mode (SCI)
Figure 11.1 Block Diagram of SCI............................................................................................. 292
Figure 11.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 304
Figure 11.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 306
Figure 11.4 Sample SCI Initialization Flowchart ....................................................................... 307
Figure 11.5 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 308
Figure 11.6 Sample Serial Transmission Flowchart ................................................................... 309
Figure 11.7 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 310
Figure 11.8 Sample Serial Reception Data Flowchart (1) .......................................................... 312
Figure 11.8 Sample Serial Reception Data Flowchart (2) .......................................................... 313
Figure 11.9 Sample Flowchart for Mode Transition during Transmission................................. 316
Figure 11.10 Sample Flowchart for Mode Transition during Reception .................................... 317
Section 12 Universal Serial Bus 2 (USB2)
Figure 12.1 Block Diagram of USB2 ......................................................................................... 320
Figure 12.2 USB Cable Connection ........................................................................................... 341
Figure 12.3 USB Cable Disconnection....................................................................................... 342
Figure 12.4 Control Transfer Stage Configuration ..................................................................... 343
Rev. 2.00, 03/04, page xxv of xxxii