H8S2172 Datasheet, PDF (176/572 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

φ
Address bus
()
,
Read
()
()
Data bus
()
Write
()
Data bus
T_p
T_r
Row address
High
High
T_c1
T_c2
T_c3
Column address
Figure 6.43 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)
6.7 Idle Cycle
6.7.1 Operation
When this LSI accesses external address space, it can insert an idle cycle (T_i) between bus cycles
in the following three cases: (1) when read accesses in different areas occur consecutively or when
an external access cycle occurs after a single address transfer, (2) when (1) occurs and a write
cycle occurs immediately after a read cycle, and (3) when (1) and (2) occur and a read cycle
occurs immediately after a write cycle. A condition for idle cycle insertion can be selected with
the IDLE1 and IDLE0 bits in BCR. The number of idle cycles to be inserted can be set from one
to four states by setting the IDLC1 and IDLC0 bits in BCR. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, etc., with a long output floating
time, and high-speed memory, I/O interfaces, and so on.
Rev. 2.00, 03/04, page 142 of 534