H8S2172 Datasheet, PDF (317/572 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 10 Watchdog Timer (WDT)
This LSI incorporates an 8-bit watchdog timer with one channel (WDT). If a system crash
prevents the CPU from writing to the timer counter, thus allowing it to overflow, the WDT can
generate an internal reset signal or an internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT is shown in figure 10.1.
10.1 Features
• Selectable from eight counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
• If the counter overflows, an internal reset or an internal NMI interrupt is generated.
Internal Timer Mode:
• If the counter overflows, an internal timer interrupt (WOVI) is generated.
WOVI
(Interrupt request signal)
Internal NMI
(Interrupt request signal)
Internal reset signal
Interrupt
control
Reset
control
Overflow
Clock
Clock
selection
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
TCNT
TCSR
Module bus
Bus
interface
Legend
TCSR : Timer control/status register
TCNT : Timer counter
WDT
Figure 10.1 Block Diagram of WDT
Rev. 2.00, 03/04, page 283 of 534