H8S2172 Datasheet, PDF (13/572 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

5.6.2 Interrupt Control Mode 1 ..................................................................................... 76
5.6.3 Interrupt Exception Handling Sequence .............................................................. 78
5.6.4 Interrupt Response Times .................................................................................... 80
5.7 Usage Notes ...................................................................................................................... 81
5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 81
5.7.2 Instructions that Disable Interrupts ...................................................................... 82
5.7.3 Interrupts during Execution of EEPMOV Instruction.......................................... 82
Section 6 Bus Controller (BSC).........................................................................83
6.1 Features............................................................................................................................. 83
6.2 Input/Output Pins .............................................................................................................. 85
6.3 Register Descriptions ........................................................................................................ 86
6.3.1 Access Control Register (ACSCR) ...................................................................... 87
6.3.2 CS Assertion Period Control Register (CSACR)................................................. 88
6.3.3 Wait Control Register (WTCR) ........................................................................... 90
6.3.4 Bus Control Register (BCR) ................................................................................ 92
6.3.5 Read Strobe Timing Control Register (RDNCR) ................................................ 93
6.3.6 DRAM Control Register (DRAMCR) ................................................................. 94
6.3.7 DRAM Access Control Register (DRACCR)...................................................... 97
6.3.8 Refresh Control Register (REFCR) ..................................................................... 98
6.3.9 Refresh Timer Counter (RTCNT)........................................................................ 101
6.3.10 Refresh Time Constant Register (RTCOR) ......................................................... 101
6.4 Bus Control ....................................................................................................................... 102
6.4.1 Area Division....................................................................................................... 102
6.4.2 Address Map ........................................................................................................ 103
6.4.3 Bus Specifications................................................................................................ 105
6.4.4 Memory Interfaces............................................................................................... 107
6.4.5 Chip Select Signals .............................................................................................. 108
6.5 Basic Bus Interface ........................................................................................................... 109
6.5.1 Data Size and Data Alignment............................................................................. 109
6.5.2 Valid Strobes ....................................................................................................... 110
6.5.3 Basic Timing........................................................................................................ 110
6.5.4 Wait Control ........................................................................................................ 119
6.5.5 Read Strobe (RD) Timing.................................................................................... 120
6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 121
6.6 DRAM Interface ............................................................................................................... 122
6.6.1 Setting DRAM Space........................................................................................... 122
6.6.2 Address Multiplexing .......................................................................................... 122
6.6.3 Data Bus............................................................................................................... 123
6.6.4 Pins Used for DRAM Interface............................................................................ 123
6.6.5 Basic Timing........................................................................................................ 124
6.6.6 Column Address Output Cycle Control ............................................................... 125
6.6.7 Row Address Output State Control...................................................................... 126
Rev. 2.00, 03/04, page xi of xxxii