R8C-22_1 Datasheet, PDF (506/549 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/22 Group, R8C/23 Group
22. Usage Notes
22.7 Notes on CAN Module
22.7.1 Reading C0STR Register
The CAN module updates the status of the C0STR register in a certain period. When the CPU and the CAN
module access to the C0STR register at the same time, the CPU has the access priority; the access from the
CAN module is disabled. Consequently, when the updating period of the CAN module matches the access
period from the CPU, the status of the CAN module cannot be updated. (See Figure 22.8)
Accordingly, be careful about the following points so that the access period from the CPU should not match the
updating period of the CAN module:
• There should be a wait time of 3fCAN or longer (see Table 22.2) before the CPU reads the C0STR register.
(See Figure 22.9)
• When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure 22.10)
Table 22.2 CAN Module Status Updating Period
3 fCAN Period = 3 x XIN (Original Oscillation Period) x Division Value of CAN Clock (CCLK)
(Example 1) Condition XIN 16 MHz CCLK: Divided by 1 3 fCAN period = 3 x 62.5 ns x 1 = 187.5 ns
(Example 2) Condition XIN 16 MHz CCLK: Divided by 2 3 fCAN period = 3 x 62.5 ns x 2 = 375 ns
(Example 3) Condition XIN 16 MHz CCLK: Divided by 4 3 fCAN period = 3 x 62.5 ns x 4 = 750 ns
(Example 4) Condition XIN 16 MHz CCLK: Divided by 8 3 fCAN period = 3 x 62.5 ns x 8 = 1.5 µs
(Example 5) Condition XIN 16 MHz CCLK: Divided by 16 3 fCAN period = 3 x 62.5 ns x 16 = 3 µs
Rev.2.00 Aug 20, 2008 Page 486 of 501
REJ09B0251-0200