R8C-22_1 Datasheet, PDF (151/549 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/22 Group, R8C/23 Group
14. Timers
Timer RA Control Register⁽⁴⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRACR
Bit Symbol
Address
0100h
Bit Name
After Reset
00h
Function
RW
Timer RA count start bit⁽¹⁾ 0 : Stops counting
TSTART
1 : Starts counting
RW
Timer RA count status flag⁽¹⁾ 0 : Stops counting
TCSTF
1 : Counting
RO
Timer RA count forcible stop When this bit is set to 1, the count is forcibly
TSTOP _bit(2)
stopped. When read, the content is 0.
RW
—
Nothing is assigned. If necessary, set to 0.
(b3) When read, the content is 0.
—
Active edge reception
0 : Active edge not received
TEDGF ^flag(3,5)
1 : Active edge received
RW
(end of measurement period)
Timer RA underflow flag^(3,5) 0 : No underflow
TUNDF
1 : Underflow
RW
—
Nothing is assigned. If necessary, set to 0.
(b7-b6) When read, the content is 0.
—
NOTES:
1. Refer to 14.1.6 Notes on Tim er RA.
2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a
reset.
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRAIOC
0101h
00h
Bit Symbol
Bit Name
Function
RW
TEDGSEL TRAIO polarity sw itch bit Function varies depending on operation mode
RW
TOPCR TRAIO output control bit
RW
TOENA TRAO output enable bit
RW
_____
TIOSEL INT1/TRAIO select bit
RW
TIPF0 TRAIO input filter select bits
RW
TIPF1
RW
—
Nothing is assigned. If necessary, set to 0.
(b7-b6) When read, the content is 0.
—
Figure 14.2 Registers TRACR and TRAIOC
Rev.2.00 Aug 20, 2008 Page 131 of 501
REJ09B0251-0200