R8C-22_1 Datasheet, PDF (224/549 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/22 Group, R8C/23 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol
Bit Name
Function
RW
Input capture/compare match [Source for setting this bit to 0]
flag A
Write 0 after read.⁽²⁾
IMFA
[Source for setting this bit to 1]
RW
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
IMFB
Input capture/compare match [Source for setting this bit to 0]
flag B
Write 0 after read.⁽²⁾
[Source for setting this bit to 1]
RW
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
IMFC
Input capture/compare match [Source for setting this bit to 0]
flag C
Write 0 after read.⁽²⁾
[Source for setting this bit to 1]
RW
When the value in the TRDi register matches w ith
the value in the TRDGRCi register.⁽³⁾
IMFD
Input capture/compare match [Source for setting this bit to 0]
flag D
Write 0 after read.⁽²⁾
[Source for setting this bit to 1]
RW
When the value in the TRDi register matches w ith
the value in the TRDGRDi register.⁽³⁾
Overflow flag
[Source for setting this bit to 0]
OVF
Write 0 after read.⁽²⁾
[Source for setting this bit to 1]
RW
When the TRDi register overflow s.
UDF
Underflow flag⁽¹⁾
This bit is disabled in the output compare function.
RW
—
Nothing is assigned. If necessary, set to 0.
(b7 - b6) When read, the content is 1.
—
NOTES:
1. Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this
bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1.
3. Including w hen the BFji bit (j = C or D) in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.56 Registers TRDSR0 to TRDSR1 in Output Compare Function
Rev.2.00 Aug 20, 2008 Page 204 of 501
REJ09B0251-0200