32182 Datasheet, PDF (50/755 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

2
2.3.5 Floating-point Status Register: FPSR (CR7)
CPU
2.3 Control Registers
b0 1
2
3
4
5
6
7
8
9 10 11 12 13 14 b15
FS FX FU FZ FO FV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31
EX EU EZ EO EV
DN CE CX CU CZ CO CV
RM
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
b
0
1
2
3
4
5
6–16
17
18
19
20
21
22
23
24
25
<After reset: H’0000 0100>
Bit Name
Function
RW
FS
Reflects the logical sum of FU, FZ, FO and FV.
Floating-point Exception Summary Bit
R–
FX
Inexact Exception Flag
Set to "1" when an inexact exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
RW
FU
Underflow Exception Flag
Set to "1" when an underflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
RW
FZ
Zero Divide Exception Flag
Set to "1" when a zero divide exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
RW
FO
Overflow Exception Flag
Set to "1" when an overflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
RW
FV
Invalid Operation Exception Flag
Set to "1" when an invalid operation exception occurs (if EIT processing
is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
RW
No function assigned. Fix to "0".
00
EX
Inexact Exception Enable Bit
0: Mask EIT processing to be executed when an inexact exception occurs. R W
1: Execute EIT processing when an inexact exception occurs.
EU
Underflow Exception Enable Bit
0: Mask EIT processing to be executed when an underflow exception
occurs.
1: Execute EIT processing when an underflow exception occurs.
RW
EZ
Zero Divide Exception Enable Bit
0: Mask EIT processing to be executed when a zero divide exception
occurs.
1: Execute EIT processing when a zero divide exception occurs.
RW
EO
Overflow Exception Enable Bit
0: Mask EIT processing to be executed when an overflow exception
occurs.
1: Execute EIT processing when an overflow exception occurs.
RW
EV
0: Mask EIT processing to be executed when an invalid operation
RW
Invalid Operation Exception Enable Bit exception occurs.
1: Execute EIT processing when an invalid operation exception occurs.
No function assigned. Fix to "0".
00
DN
Denormalized Number Zero Flush Bit
(Note 2)
0: Handle the denormalized number as a denormalized number.
1: Handle the denormalized number as zero.
RW
CE
Unimplemented Operation
Exception Cause Bit
0: No unimplemented operation exception occurred.
1: An unimplemented operation exception occurred. When the bit is
set to "1", the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
CX
Inexact Exception Cause Bit
0: No inexact exception occurred.
1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
R (Note 3)
2-5
32182 Group User’s Manual (Rev.1.0)