32182 Datasheet, PDF (243/755 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

9
DMAC
9.3 Functional Description of the DMAC
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing
00
01
10
Software start or one DMA7
When any data is written to the DMA5 Software Request Generation Register
transfer completed
(software start) or when one DMA7 transfer is completed (cascade mode)
All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode)
Serial I/O2 (reception completed) When serial I/O2 reception is completed
11
Extended DMA5 transfer request The source selected by the DMA5 Channel Control Register 1 (DM5CNT1)
source selected
REQESEL5 bits (see below)
REQESEL5 DMA Transfer Request Source
0000
MJT (TIN20 input signal)
0001
Settings inhibited
0010
Settings inhibited
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
1010
|
1111
Settings inhibited
DMA Transfer Request Generation Timing
When MJT TIN20 input signal is generated
–
–
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6 DMA Transfer Request Source DMA Transfer Request Generation Timing
00
01
10
Software start
When any data is written to the DMA6 Software Request Generation Register
Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
Settings inhibited
–
11
Extended DMA6 transfer request The source selected by the DMA6 Channel Control Register 1 (DM6CNT1)
source selected
REQESEL6 bits (see below)
REQESEL6 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000
One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode)
0001
Settings inhibited
–
0010
Serial I/O1 (reception completed) When serial I/O1 reception is completed
0011
0100
0101
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
0110
0111
1000
1001
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
9-30
32182 Group User’s Manual (Rev.1.0)