32182 Datasheet, PDF (424/755 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

12
Serial I/O
12.2 Serial I/O Related Registers
12.2.2 SIO Transmit Control Registers
SIO0 Transmit Control Register (S0TCNT)
SIO1 Transmit Control Register (S1TCNT)
SIO2 Transmit Control Register (S2TCNT)
SIO3 Transmit Control Register (S3TCNT)
<Address: H'0080 0110>
<Address: H'0080 0120>
<Address: H'0080 0130>
<Address: H'0080 0140>
b0
0
b
0, 1
2, 3
4
5
6
7
1
2
3
4
5
6
CDIV
TSTAT TBE
0
0
1
0
0
1
Bit Name
No function assigned. Fix to "0".
CDIV
BRG count source select bit
No function assigned. Fix to "0".
TSTAT
Transmit status bit
TBE
Transmit buffer empty bit
TEN
Transmit enable bit
b7
TEN
0
<After reset: H’12>
Function
RW
00
b2 b3
0 0: Select f(BCLK)
0 1: Select f(BCLK) divided by 8
1 0: Select f(BCLK) divided by 32
1 1: Select f(BCLK) divided by 256
RW
00
0:Transmission stopped and no data in transmit buffer register R –
1:Transmitting now or data present in transmit buffer register
0:Data present in transmit buffer register
1: No data in transmit buffer register
R–
0: Disable transmission
1: Enable transmission
RW
(1) CDIV (baud rate generator count source select) bits (Bits 2–3)
These bits select the count source for the Baud Rate Generator (BRG).
Note: • If f(BCLK) is selected as the count source for the BRG, care must be taken when setting the
BRG so that the baud rate will not exceed the maximum transfer speed. For details, see the
section in which the BRG register is explained.
(2) TSTAT (Transmit Status) bit (Bit 5)
[Set condition]
This bit is set to "1" by a write to the transmit buffer register while transmission is enabled.
[Clear condition]
This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no data
exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit.
(3) TBE (Transmit Buffer Empty) bit (Bit 6)
[Set condition]
This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift register
and the transmit buffer register is thereby emptied. This bit is also set by clearing the transmit enable bit
to "0".
[Clear condition]
This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while transmission
is enabled (TEN = "1").
(4) TEN (Transmit Enable) bit (Bit 7)
Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0". If this bit is cleared to
"0" while transmitting data, the transmit operation stops.
12-13
32182 Group User's Manual (Rev.1.0)