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R1EV5801MB_16 Datasheet, PDF (5/22 Pages) Renesas Technology Corp – 1M EEPROM (128-Kword × 8-bit)Ready Busy and RES function | |||
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R1EV5801MB Series
AC Characteristics
Test Conditions
ï· Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin)
ï· Input rise and fall time: ï£ 20 ns
ï· Output load: 1TTL Gate +100 pF
ï· Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
Parameter
Symbol
Min
Address to output delay
tACC
ï¾ï
CE to output delay
tCE
ï¾ï
OE to output delay
tOE
10
Address to output hold
tOH
0
OE (CE) high to output float*1
tDF
0
RES low to output float*1
tDFR
0
RES to output delay
tRR
0
Max
150
150
75
ï¾ï
50
350
450
(Ta = -40 to +85ï°C, VCC = 4.5 V to 5.5 V)
Unit
ns
ns
ns
ns
ns
ns
ns
Test conditions
CE = OE = VIL, WE = VIH
OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
Write Cycle
Parameter
Symbol Min*2 Typ Max Unit Test conditions
Address setup time
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
Data setup time
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
Data latch time
Byte load cycle
Byte load window
Write cycle time
Time to device busy
Write start time
Reset protect time
Reset high time*5
tAS
0
ï¾ï
ï¾ï ns
tAH
150
ï¾ï
ï¾ï ns
tCS
0
ï¾ï
ï¾ï ns
tCH
0
ï¾ï
ï¾ï ns
tWS
0
ï¾ï
ï¾ï ns
tWH
0
ï¾ï
ï¾ï ns
tOES
0
ï¾ï
ï¾ï ns
tOEH
0
ï¾ï
ï¾ï ns
tDS
100
ï¾ï
ï¾ï ns
tDH
10
ï¾ï
ï¾ï ns
tWP
0.250 ï¾ï
30
µs
tCW
0.250 ï¾ï
30
µs
tDL
300
ï¾ï
ï¾ï ns
tBLC
0.55 ï¾ï
30
µs
tBL
100
ï¾ï
ï¾ï µs
tWC
â
ï¾ï 10*3 ms
tDB
120 ï¾ï
tDW
150*4 ï¾ï
ï¾ï ns
ï¾ï ns
tRP
100
ï¾ï
ï¾ï µs
tRES
1
ï¾ï
ï¾ï µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer
driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically
completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100ï¥ tested.
6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE.
7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE.
8. See AC read characteristics.
R10DS0209EJ0200 Rev.2.00
May 12, 2016
Page 5 of 20
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