HD74LS107A Datasheet, PDF(5/7 Page) Hitachi Semiconductor – Dual J-K Negative-edge-triggered Flip-Flops(with Clear)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD74LS107A Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Dual J-K Negative-edge-triggered Flip-Flops(with Clear)

◁

HD74LS107A

Waveforms 1

Clock

10%

tTLH

tTHL

90% 90%

tw(L)

1.3 V 1.3 V

10%

tw(H)

tPLH

1.3 V 1.3 V

tPHL

1.3 V

tPHL

1.3 V

tPLH

VOH

VOL

1.3 V

Note: Clock input pulse: tTLH â¤ 15 ns, tTHL â¤ 6 ns, PRR = 1 MHz,

duty cycle = 50% and: for fmax, tTHL tTHL â¤ 2.5 ns.

1.3 V

VOH

VOL

Waveforms 2

Clear

Clock

tTHL

tTLH

90%

1.3V

10%

tw (CLR)

90%

1.3V

10%

tPHL

1.3V

tPLH

tTLH

tTHL

10%

90% 90%

1.3V 1.3V

tw (CK) â¥ 20ns

10%

VOH

VOL

VOH

1.3V

VOL

Note: Clear and clock input pulse: tTLH â¤ 15 ns, tTHL â¤ 6 ns, PRR = 1 MHz.

Rev.3.00, Jul.13.2005, page 5 of 6

▷