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HD74LS107A Datasheet, PDF (4/7 Pages) Hitachi Semiconductor – Dual J-K Negative-edge-triggered Flip-Flops(with Clear) | |||
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HD74LS107A
Testing Method
Test Circuit
1. Æmax, tPLH, tPHL, (ClockâQ, Q)
Input 4.5V
VCC Output Q
P.G.
Zout=50â¦
J
CK
K
CLR
Q
Output Q
Q
Load circuit 1
RL
CL
Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. tPHL (ClearâQ), tPLH (ClearâQ)
VCC Output Q
P.G.
Zout=50â¦
P.G.
Zout=50â¦
4.5V
Input
Input
J
CK
K
CLR
Q
Output Q
Q
Load circuit 1
RL
CL
Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.13.2005, page 4 of 6
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