HD74LS107A Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual J-K Negative-edge-triggered Flip-Flops(with Clear)

HD74LS107A
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300
Rev.3.00
Jul.13.2005
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS107AP
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
HD74LS107AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B
FP
(FP-14DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Pin Arrangement
1J 1
1Q 2
1Q 3
1K 4
2Q 5
2Q 6
GND 7
CLR J
Q _CK
Q
K
Q
K
Q ^CK
CLR J
(Top view)
14 V_CC
13 _1CLR
12 _1CK
11 _2K
10 _2CLR
9 _2CK
8 2J
Function Table
Inputs
Outputs
Clear
Clock
J
K
Q
Q
L
X
X
X
L
H
H
↓
L
L
Q_O
Q_O
H
↓
H
L
H
L
H
↓
L
H
L
H
H
↓
H
H
Toggle
H
H
X
X
Q_O
Q_O
Notes: H; high level, L; low level, X; irrelevant
↓; transition from high to low level
Q; level of Q before the indicated steady-state input conditions were established.
Q; complement of Q_O or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
Rev.3.00, Jul.13.2005, page 1 of 6